In recent years, many electronic and optoelectronic components have been produced that are either based on semiconductor nanowires (Y. Cui and C. M. Lieber, Science, Vol. 291, p. 851, 2001; X. Duan and C. Niu et al., Nature, Vol. 425, p. 274, 2003; Y. Cui et al., Nano Lett. Vol. 3, p. 149, 2003; Samuelson et al., Physica E 21, p. 560, 2004; E. Bakkers et al., Nature Materials, Vol. 3, p. 769, 2004) or based on carbon nanotubes (Ph. Avouris, Accounts of Chemical Research, Vol. 35, p. 1026, 2002; A. Javey et al., Nature, Vol. 424, p. 654, 2003; A. Javey et al., Nature Materials, Vol. 1, p. 241, 2002; A. Javey et al., Nano Lett., Vol. 4, p. 447, 2004; R. V. Siedel et al., Nano Lett., Vol. 5, p. 147, 2005; J. A. Misewich et al., Science, Vol. 300, p. 783, 2003) and the benefit of such nanostructures has been widely demonstrated. In particular, with regard to silicon nanowires, carrier (hole) mobilities of around 1300 cm2/Vs have been obtained (Y. Cui et al., Nano Lett., Vol. 3, p. 149, 2003), which is quite remarkable, whereas with regard to semiconducting carbon nanotubes (also called s-CNTs) mobilities of around 3000 cm2/Vs (again for holes) have been published (A. Javey et al., Nature Materials, Vol. 1, p. 241, 2002; A. Javey et al., Nano Lett., Vol. 4, p. 447, 2004). Recently, light-emitting diodes based on s-CNTs have been produced (J. A. Misewich et al., Science, Vol. 300, p. 783; 2003).
However, although the benefit of devices based on nanostructures is incontestable, their fabrication on a large scale and their integration into complex circuits is impossible at the present time, since no recognized method exists for handling and organizing a large number of nanowires and/or s-CNTs reliably and reproducibly.
Various techniques have been proposed for collectively organizing nanowires/s-CNTs on a surface. These techniques are based either on chemical grafting of the surface and/or of the nanowire (M. Hazani et al., Chemical Physics Letters, Vol. 391, pp. 389-392, 2004) or on the use of Longmuir-Blodgett-type layers (Song Jin et al. Nano Letters, Vol. 4, pp. 915-919, 2004) or on growth in porous alumina templates (K. K. Lew and J. M. Redwing, Journal of Crystal Growth, Vol. 254, pp. 14-22, 2003). According to this technique, a membrane 2 is produced by anodic oxidation of an aluminum substrate 1. Next, metallic catalytic elements 3i of the gold type are deposited as illustrated in FIG. 1. Starting from these catalytic elements, single crystals 4i of semiconductor material are grown from the vapor phase, thanks for example to a stream of silane, Fv, using the known VLS (vapor-liquid-solid) method. The growth of single crystals using this method was very widely studied during the 1960s (“Whisker Technology” by R. S. Wagner, Wiley, pp. 47-119, 1970). The principle of this method is illustrated in FIG. 2.
More precisely, a spot of gold is placed on the surface of a substrate and the assembly is heated to 400° C. in the presence of silane gas SiH4. The latter will slightly decompose and the silicon (Si) atoms liberated will alloy with the gold (Au) on the surface so as to form the alloy element 3′i. According to the gold/silicon phase diagram illustrated in FIG. 3, the composition of the alloy will vary toward the eutectic composition as the gold is progressively enriched with silicon and there will be surface melting as soon as the liquidus drops below 400° C. The surface of the liquid, having adsorption sites that are unsaturable, thus becomes a place for preferential decomposition of the SiH4 molecules. As a result, the entire gold spot will rapidly reach the eutectic composition and melt. The composition of the liquid will continue to change beyond the eutectic composition, where the liquidus goes back above 400° C. Excess silicon is therefore expelled at the liquid/solid interface, so as to maintain the thermodynamic equilibrium, and the drop of eutectic liquid progressively rises on the expelled crystal, taking the form of a whisker with a diameter equal to that of the drop, allowing the subsequent growth of the silicon nanowire 4i. 
This technique, extensively developed in the 1960s, was recently used for growing silicon nanowires from gold nanoparticles deposited beforehand on a substrate (Y. Cui et al., Applied Physics Letters, Vol. 78, pp. 2214-2217, 2001). Nanowires with a diameter between 10 and 20 nm may be routinely fabricated using this method. Moreover, field-effect transistors produced from such nanowires exhibit remarkable transport properties—hole (p) mobilities that may be up to 1300 cm2/Vs having been measured (Y. Cui et al., Nano Letters, Vol. 3, pp. 149-152, 2003).